The present invention relates to a semiconducting carbon nanotube, a method for positioning the carbon nanotube, a field effect transistor (FET) made using the carbon nanotube, and a semiconductor device.
Ever since the year 1947 when a first semiconductor transistor was invented, the degree of integration of silicon microelectronics has grown substantially exponentially. Such growth, however, is not expected to continue in the near future. In particular, as the scale of integration approximates the nanometer order, the structure is reaching a physical limit of reliably achieving a desired function. With the increasing scale of integration, the cost of manufacture is also increasing exponentially, thereby inhibiting realization of higher integration.
As the technology that can overcome the limitation imposed by the principle of the silicon technology, the field of molecular electronics has drawn much attention. According to the molecular electronics, a monomolecular device can be fabricated at relatively low cost by self-alignment technology.
In the field of molecular electronics, molecular structures such as fullerenes and carbon nanotubes are increasingly attracting attentions. In particular, single-walled carbon nanotubes (SWNTs), which are rolled graphene sheets having diameters on the nanometer order, have been vigorously investigated as to their properties desirable in the field of electronics ever since their discovery in early 1990's.
SWNTs can show metallic or semiconducting electrical behavior depending on the angle and/or chirality of the spiral lattices of carbon molecules constituting the tube. The electrical performance of SWNTs is expected to surpass that of the best metal or semiconductor.
In 1998, a field-emission transistor (FET) incorporating a single SWNT was realized at room temperature (refer to Trans, S. J. et al., Nature, 1998, vol. 393, p. 49). An inverter, which is the simplest logical gate, was realized using a unipolar or complementary FET incorporating one or two carbon nanotubes. Other logical gates, such as NOR, AND, and static RAMs (SRAMs), were also fabricated using a complementary or multi-complementary mode. Ring oscillators realizing an oscillation frequency of 220 Hz were fabricated using arrays of p- or n-type carbon nanotube FETs (refer to Bachtold, A. et al., Science, 2001, vol. 294, p. 1317, and Derycke, V. et al., Nano Letters, 2002, vol. 2, p. 929).
Basic logical circuits incorporating transistors including SWNTs described above are mainly fabricated by two techniques. One is to disperse SWNTs in a solvent so that the carbon nanotubes can be positioned by scanning with an atomic force microscope (AFM) at the corresponding electrodes patterned in advance (refer to Trans, S. J. et al. and Bachtold, A. et al. above).
In this technique (first technique), SWNTs having a diameter of about 1 nm fabricated by laser abrasion are typically suspended in dichloroethane and this suspension is distributed on a wafer so that the SWNTs can be placed on gate electrodes using an AFM. Subsequently, selective deposition of Au is performed by lithography to form contact electrodes and leads on these nanotubes. According to an example of this technique disclosed in Martel, R. et al., Applied Physics Letters, 1998, vol. 73, p. 2447, a hole mobility of 20 cm2/(V·s) is achieved in a back-gate structure.
Furthermore, a top-gate FET achieving a mutual conductance as high as 2,321 S/m by incorporating a carbon nanotube (CNT) as the gate electrode has been reported (Wind, S. J. et al., Applied Physics Letters, 2002, vol. 80, p. 38).
The other technique (second technique) is to directly deposit SWNTs by chemical vapor deposition (CVD) on electrode patterns formed in advance. Examples thereof are found in Javey, A. et al., Nature, 2003, vol. 424, p. 654 and in Tseng, Y. et al., Nano Letters, 2004, vol. 1, p. 123.
Transistors fabricated by this technique exhibit a mutual conductance as high as 6,000 S/m and a carrier mobility as high as 3,000 cm2/(V·s), which are important properties for transistors. These values are one digit larger than those of silicon semiconductors.
In particular, a transistor prepared by this technique achieves a carrier mobility as high as 79,000 cm2/(V·s) by incorporating a semiconductor CNT 300 μm in length, as reported in Durkop, T. et al., Nano Letters, 2004, vol. 4, p. 35.
The first technique that uses an AFM is hardly practicable since it concerns manual placement of a large number of CNTs on devices. Its application to semiconductor devices, such as memories of central processing unit (CPU) chips, is difficult.
The second technique that employs CVD is a high-temperature process. Thus, accurate positioning of CNTs on a large number of electrodes is difficult. The second technique is rarely suitable for integrated circuit applications. In fact, an actual case of mounting SWNTs onto part of a silicon metal oxide semiconductor (MOS) by CVD reported low alignment accuracy, i.e., that only 1% of about 2,000 CNTs functioned as back gates (refer to Tseng, Y. et al., Nano Letters, 2004, vol. 4, p. 123).